Fabrication of micro and nano scale structures including those used in integrated circuits, is limited by the resolution of the lithography process used to define the dimensions of the feature as well as by the physical and chemical properties of the materials the features are to be fabricated from. For example, sidewall image transfer techniques, which can form features having sub-lithographic dimensions, are not compatible with non-volatile materials. In another example, many materials are difficult or impossible to deposit in conformal layers so conventional spacer processes cannot be used. In other cases, the methods of fabricating features having sub-lithographic dimensions require expensive equipment or are very time-consuming. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.